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Time-Interleaved ADCs
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Clock-skew errors in time-interleaved ADCs importantly degrade the linearity of such converters. These nearly constant but unknown errors lead time-interleaved ADCs into periodical non-uniform sampling. There are some techniques of facing clock-skew errors: two-ranks sample-and-hold, channel randomization, global passive sampling, clock-edge reassignment, all-digital and all-analog calibration techniques. We propose a new kind of mixed-signal clock-skew calibration technique that distinguishes itself by the simplicity of its analog components while keeping the inherent robustness of digital clock-skew detections. A demonstrator shows the feasibility of our technique by correcting initial clock-skews of thousands of picoseconds with a granularity of 1.8 picoseconds. The theoretical work together with the experimental details developed in this book offer readers from the mixed-signal circuit field a comprehensive way to deal with clock-skew errors in future time-interleaved ADCs.
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