Contact
How to shop
Delivery
Shopping guide
English
191 b
Up to 30 days for returns
Customers also purchased
/
Paperback
8 539
Ft
/
Paperback
2 840
Ft
/
Hardback
11 972
Ft
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today's digital designs. "ASIC and FPGA Verification: A Guide to Component Modeling" expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. This book provides numerous models and a clearly defined methodology for performing board-level simulation. It covers the details of modeling for verification of both logic and timing. This is the first book to collect and teach techniques for using VHDL to model 'off-the-shelf' or 'IP' digital components for use in FPGA and board-level design verification.
About the book
English
Give this book today
It's easy
1 Add to cart and choose Deliver as present at the checkout 2 We'll send you a voucher 3 The book will arrive at the recipient's addressYou might also be interested in
/
Paperback
10 557
Ft
/
Paperback
6 347
Ft
/
Paperback
17 218
Ft
/
Paperback
11 204
Ft
Hi! I'm Libroamiko, your book advisor.
How can I help you?