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Pipelined Multi-core MIPS Machine

Name: Pipelined Multi-core MIPS Machine
Brand: Springer International Publishing AG
SKU: 09090222
Price: 20346 HUF
Availability: InStock
Author: Silvia Melitta Muller
ISBN: 9783319139050

Hardware Implementation and Correctness Proof

Silvia Melitta Muller

Wolfgang J. Paul

Language

English

Book Paperback

Libristo code: 09090222

Publishers Springer International Publishing AG, December 2014

This monograph is based on the third author's lectures on computer architecture, given in the summer... Full description

Libristo code: 09090222

136 b

20 346 Ft

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This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.§The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future.§Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work.